CROSSEC

Overview

As embedded electronics become pervasive across consumer devices, critical infrastructures, and defense systems, hardware security has emerged as a cornerstone of modern cybersecurity. Cryptographic circuits are increasingly exposed to sophisticated hardware attacks — including side-channel analysis (SCA), fault injection (FI), piracy, and hardware Trojans — that exploit implementation-level vulnerabilities rather than mathematical weaknesses. While numerous countermeasures exist to mitigate each type of attack, they are traditionally designed and evaluated in isolation. However, recent research shows that combining countermeasures can introduce unexpected cross-effects, where a defense against one attack inadvertently opens the door to another.

CROSSEC addresses this critical gap by studying the composability of hardware security countermeasures and developing a methodology to assess their interactions throughout the entire IC design flow.

Objectives

Following a security-by-design philosophy, CROSSEC aims to create a secure design methodology for the early stages of integrated circuit design that explicitly accounts for the cross-security implications of composed countermeasures. Specifically, the project will:

1. Study the composability of widely used countermeasures across multiple abstraction levels (RTL, gate-level, physical layout).
2. Develop quantitative metrics for security evaluation that account for composability and its impact on area, performance, and power consumption.
3. Analyze and select design tools — prioritizing open-source and in-house solutions — to support the proposed methodology.
4. Create diagnostic tools to identify vulnerable sub-blocks and guide the design of effective countermeasures.

Validate the methodology through the design and fabrication of an ASIC demonstrator incorporating diverse cryptographic use cases.

Expected Contributions

• A taxonomy of cross-effects generated by the composition of secure-by-design countermeasures.
• Novel metrics and tools for pre-silicon security assessment supporting composability analysis.
• A new design methodology that integrates cross-effect considerations throughout the complete design flow cycle.

Validation in both classical and post-quantum cryptographic circuits, addressing the emerging challenges posed by quantum-resistant schemes.